Can adaptive inductor and frequency management improve integrated power converter efficiency?

Fixed inductance is optimal only at one load point

A conventional buck converter fixes its inductance and switching frequency to maximize efficiency at a nominal operating point. Real workloads in edge and high-performance computing are strongly time-varying, so away from that point the design wastes conduction loss at heavy load and switching loss at light load. The paper frames this as a mismatch between inductance, switching frequency, and load current.

The loss physics explains the trade-off. Inductor DC winding resistance produces I²R conduction loss that dominates at high load because of its quadratic current dependence, while AC core, skin, and proximity losses depend more weakly on load. Lowering DC resistance favors fewer turns or thicker conductors, which reduces inductance; raising inductance suppresses ripple and AC loss but increases winding resistance and size. Switching devices add conduction loss that grows quadratically with current and switching loss that grows with both current and frequency, so a minimum-loss design must jointly account for switch and inductor losses.

A tapped air-core spiral adds inductance as a free variable

The proposed architecture combines a reconfigurable inductor, a switching-frequency control mechanism, and a buck converter. The inductor is a planar, air-core square spiral whose winding is divided into series sub-inductors with intermediate nodes exposed as taps. A network of three configuration switches selects which tap feeds the converter, so the effective number of active turns, and therefore the effective inductance, can be adjusted at runtime. The specific realization uses four series sub-inductors and switch-selected taps spanning two to five turns.

The air core is deliberate: it eliminates core and hysteresis losses, avoids saturation, and yields a load-independent, linear inductance. The paper reports the resulting states as 40.5 nH at 2 turns, 71.4 nH at 3 turns, 103.6 nH at 4 turns, and 136.8 nH at 5 turns, with DC resistance rising from 27.28 mΩ to 61.9 mΩ across the same range. Because all states live in one magnetic component, the design avoids duplicated magnetics and their interconnects, which matters for package-embedded integration. The reconfiguration principle is described as architecture-agnostic, so the square spiral is one convenient realization rather than a requirement.

Loss models, FEM, and a lookup table set the policy

The design methodology integrates physics-based analytical modeling, finite element method (FEM) simulations, and an optimization framework to find preferred operating points across the load range. The objective is to minimize total power loss over a target load-current range, including both inductor and switching losses, while satisfying inductor current ripple and form factor constraints. The resulting configurations are stored in a lookup table and applied in real time through a low-overhead control scheme.

The controller is implemented in Verilog-A and is expected to add negligible power overhead relative to the power stage: 40 logic gates and 24 µW in a TSMC 28 nm node. Duty cycle is adjusted as a function of load current using high-side and low-side switch on-resistances extracted from datasheets, and switching frequency is tuned from the prior analytical optimization. The reconfigurable inductor itself is characterized in ANSYS Q3D to extract inductance, resistance, and parasitics, and the full converter is simulated in Cadence Virtuoso with Spectre and Verilog-A models.

Inductance reconfiguration drives most of the improvement

The paper separates the two adaptation mechanisms against the best valid fixed configuration, 4 turns at 10 MHz. Adapting switching frequency alone lowered average power loss by 4.5%, raising average efficiency from 75.3% to 76.3%. Adding inductance reconfiguration reduced average loss by a further 21.8%, reaching 79.6%. Overall, average power loss fell 25.4%, and efficiency improved by +1.7 percentage points at light load and +7.5 percentage points at 6 A, averaging +4.3 percentage points across the 1–6 A range.

The authors attribute the dominant share to inductance reconfiguration, with its benefit growing at high load as inductor conduction loss becomes dominant. In the targeted package-level implementation, inductor DC losses account for up to 30% of total power loss because of the deliberately compact 200 µm air-core winding and the ≤50% ripple budget. The paper presents this as a limitation of compact embedded inductors rather than of the framework, which it says is independent of the specific converter implementation.

Fixed-turn rivals fail ripple or CCM constraints

The comparison is designed to isolate inductance reconfiguration. Each fixed-turn converter from 2 to 5 turns is individually optimized to about 84% peak efficiency and, like the proposed system, is permitted to adapt its switching frequency with load. The baselines therefore already represent frequency-adaptive converters and differ from the proposed system only in that their inductance stays fixed.

In circuit simulation over a 1 A to 6 A ramp at 6 V-to-1 V, the adaptive system reached 78.65% average efficiency, 85.88% maximum at 1.75 A, and 73.96% minimum at 6 A, with 46% maximum ripple. The 2-turn fixed converter achieved higher average efficiency at 80.17% but exited CCM below 1.05 A and violated the ripple constraint below 2.2 A. The 3-turn fixed converter violated the 50% ripple constraint below 1.21 A. The 4-turn and 5-turn fixed designs stayed valid but trailed the adaptive system in average efficiency. Analytical predictions reproduced the same trends and ranking, with threshold currents shifting because of second-order effects captured only in simulation, such as device output capacitance, gate-charge dynamics, dead-time and body-diode conduction, finite output capacitance, and interconnect parasitics.

Hysteresis control guards CCM during fast load steps

Because the controller senses load with some latency, fast transients can temporarily push the converter out of CCM. The paper introduces a hysteresis-based control strategy to mitigate these temporary CCM violations and derives a closed-form entry-margin condition under which continuous conduction is guaranteed for a bounded load slew rate.

Under a 1 ms bursty load profile, the hysteresis-based adaptive converter reduced average power loss by 18.8% versus the best valid fixed configuration (4 turns at 10 MHz) and by 26.6% versus the worst valid one (5 turns at 10 MHz). The nominal adaptive converter without hysteresis achieved larger reductions of 30.4% and 32% respectively, but the paper notes that this configuration violates the ripple constraint even at the maximum 10 MHz switching frequency, rendering it unsuitable for the specified design requirements. The hysteresis mechanism therefore trades some loss reduction for constraint compliance.

Package-density droop approaches PCB-level designs

To compare across integration levels, the paper defines a per-phase efficiency droop figure of merit: peak efficiency minus maximum-load efficiency, multiplied by phase count, divided by the load-current span between those points. Roomier PCB designs achieve low droop of 0.35 to 2.44 pp/A because board area permits large, low-DCR, high-inductance windings. Package- and interposer-integrated regulators show substantially higher values, at 4.96 pp/A on package and 15.5 to 137 pp/A on interposer, with the upper end inflated by a small load span.

The proposed converter reaches as low as 2.8 pp/A per phase single-phase and 2.72 pp/A per phase in a four-phase variant, which the authors describe as PCB-comparable droop at package density. The most directly comparable reference is a package-embedded four-phase solenoid integrated voltage regulator evaluated with the same analytical efficiency modeling framework over a comparable load range. That reference peaks at about 74% at 5 A and falls to about 67.8% at 10 A at a 5:1 conversion ratio, a FoM of 4.96 pp/A per phase, versus 2.72 pp/A per phase for the proposed four-phase converter at 6:1, which peaks at 86.84% at 7 A and reaches 83.44% at 12 A. The paper cautions that the table provides quantitative context rather than a definitive ranking, since conversion ratio, integration level, switching frequency, and magnetic implementation also influence both efficiency and the FoM.

The advantage holds where ripple and CCM bind

The decisive comparison is not peak efficiency, which all configurations approach, but which designs remain valid across the load range. The adaptive system's value comes from satisfying the 50% ripple budget and CCM operation while the 2-turn and 3-turn fixed alternatives violate one or both constraints at light load, and while the 4-turn and 5-turn fixed designs stay valid but lose more power. The paper's own framing is that the adaptive approach reuses one magnetic structure, raising effective inductance at light load and reconfiguring for lower inductance and DCR at heavy load.

Two boundaries matter for interpreting this. First, the headline 4.5 percentage-point average efficiency gain and up to 32% average power loss reduction come from simulation, not measured silicon, and the analytical and circuit evaluations use different load excitations, a synthetic bursty profile versus a deterministic ramp, so they are not intended for one-to-one numerical comparison. Second, the four-phase comparison against the package-embedded reference is a simulated apples-to-apples comparison under shared modeling assumptions, which the authors argue makes the relative FoM more robust than cross-paper efficiency comparisons. The most useful takeaway is the priority the paper establishes: inductance reconfiguration, not frequency adaptation alone, carries the dominant share of the loss reduction, and its benefit grows at high load where inductor conduction loss dominates.

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