Can Model Predictive Control Policies Be Implemented with Fully Analog Circuits?

Why standard MPC hardware struggles at high switching frequency

Model predictive control (MPC) chooses each control input by solving an optimization problem over a predicted future trajectory, which lets it handle constraints but makes real-time implementation demanding. The paper states that typical MPC implementations need analog-to-digital converters, digital-to-analog converters, and a computing device, adding cost and circuit area, and that solving a quadratic program at every iteration is infeasible for systems with fast dynamics.

Explicit MPC removes the online optimization: the control law is computed offline as a piecewise affine (PWA) function, so the input is selected from a set of affine expressions depending on which region the measured parameter vector falls into. The paper notes that this still requires digital hardware, and that when the PWA function has many regions, storing its parameters and identifying the active region can be computationally expensive. The authors cite prior explicit MPC work on buck converters as an example of these difficulties.

A third route is custom analog hardware. The paper contrasts a field-programmable gate array implementation that still needs analog-to-digital and digital-to-analog conversion with an analog circuit that solves the quadratic program directly but whose applicability is limited by circuit complexity. The gap the paper targets is a fully analog controller that avoids both conversion overhead and excessive circuit complexity.

Shrinking the explicit MPC law from 19 regions to 2

The design starts from the standard explicit MPC result: over a polytope of admissible parameters, the optimal input is a continuous PWA function defined on full-dimensional polytopic regions. Because each region and each inequality maps to circuit components, the number of regions directly sets hardware complexity. The paper therefore applies four reduction techniques in sequence, from the highest to the lowest abstraction level: move blocking, which modifies the optimization problem and defines the initial partition; non-disjoint optimal merging of regions sharing the same affine law; hyperplane separation of saturated regions; and removal of inequalities that are trivial because practical parameters always lie inside the user-specified polytope.

For the buck converter with a ceramic capacitor, the unreduced policy has 19 regions (7 unsaturated, 12 saturated) and 9 unique affine functions. Move blocking with a control horizon of 2 cuts this to 7 regions and 4 unique affine functions; optimal merging gives 5 regions; hyperplane separation leaves only 2 unsaturated regions with 2 unique unsaturated affine functions; and removing trivial inequalities leaves 4 non-trivial inequalities, one of them shared. The number of regions that must be checked drops from 19 to 2, an 89% reduction.

The paper compares this with a prior explicit MPC design for buck converters that reported an increase from 3 to 7 regions when switching frequency rose from 4 kHz to 10 kHz. The authors argue that such growth would produce an overly complex control law at their target of 500 kHz, whereas their reduced design keeps only 4 regions at that frequency.

How comparators, adders, and a multiplexer select the control law

The circuit implements the PWA policy with four building blocks: generalized adders, comparators, a logic gate network, and an analog multiplexer, followed by a sample-and-hold circuit to avoid inter-sample oscillation of the control input. Each unique unsaturated affine function is computed online by a generalized adder, which forms a weighted sum of the measured parameter voltages plus a constant offset voltage. Comparators evaluate the scalar inequalities that define region membership, producing Boolean signals.

The logic network combines those membership signals into a selection signal for the multiplexer. The multiplexer has one input per unique unsaturated affine function plus two constant inputs for the saturated lower and upper bounds, so the selected voltage is either an affine expression of the states and disturbances or a saturation limit. The paper's truth table for the buck case reduces the selection logic to four gates: one AND, one OR, one NOR, and one NOT.

For the buck converter, the reduced policy needs a four-channel multiplexer, 2 generalized adders, and 5 comparators (4 for the non-trivial region inequalities, with one shared, and 1 for the affine separator). The paper reports that implementing the same controller with the approach of the prior analog quadratic-program solver would require 8 operational amplifiers, while this architecture uses only 2.

Replacing an observer with a weighted-sum state estimate

The buck controller needs the inductor current, the capacitor voltage, the load current, and the input voltage. The inductor current is sensed with a 10 mΩ shunt resistor and a current-sense amplifier, giving an overall gain of 0.2 V/A. The capacitor voltage, however, is not directly accessible because of the capacitor's equivalent series resistance, so the paper derives an algebraic estimator instead of a conventional observer.

Starting from Kirchhoff's current law at the output node, the estimator expresses the capacitor voltage as a weighted sum of the measured inductor current, the measured output voltage, and an estimate of the load current. The load-current estimate uses a low-cost analog estimator from prior work. Because the estimate requires only weighted sums, the paper argues it simplifies the design relative to an observer-based strategy and enables a low-cost analog implementation. When the capacitor series resistance is much smaller than the load resistance, the estimator reduces to using the output voltage directly as the estimate of the capacitor voltage.

Faster settling than voltage-mode control at equal undershoot

The paper validates the design in two simulation settings: Monte Carlo simulations in Matlab-Simulink with parametric uncertainty, and circuit-level simulations in LTSpice using manufacturer models of the commercial components. The Monte Carlo study treats the load resistance, inductance, capacitance, and capacitor series resistance as uniformly distributed random variables within their stated intervals, runs 500 random cases, and covers both ceramic and electrolytic capacitors.

The most decision-relevant comparison is against standard voltage-mode control (VMC) at a 500 kHz switching frequency, tested across 3 load resistance values (1, 3, and 5 Ω) and 3 supply voltages (40, 50, and 60 V), with a 10 A output-current pulse lasting 0.2 ms. At the current rising edge, the undershoot is comparable: 2.4% for VMC and 2.6% for the analog explicit MPC. The settling time differs sharply: 2.5 µs for the analog controller versus 10 µs for VMC. At the falling edge, both show an average overshoot of 6.2%, but settling takes 42 µs for the analog controller while VMC exceeds 200 µs. The paper reports these results as consistent across the supply-voltage and load configurations tested.

The duty-cycle traces show the analog controller saturating the duty command to reject the disturbance quickly, while the VMC response is more conservative. Both controllers show a small steady-state tracking error of at most 10 mV in all simulations. For the analog controller, the paper attributes this error to the uncertain load value, model linearization error, and rounding of resistors to standard E-series values; for VMC, finite operational-amplifier gain prevents the theoretical zero error of its integral action.

The 500 kHz claim rests on latency and component models

The reported 500 kHz sampling rate is tied to the circuit's latency. The paper states that the design's latency substantially improves on the 6 µs reported for the prior analog quadratic-program solver, attributing the improvement to the absence of slew-rate limitations, and also improves on existing digital MPC implementations for buck converters. The paper adds that the prior analog approach and a field-programmable gate array approach cannot operate at the target 500 kHz; simulations at 100 kHz, a frequency compatible with the 6 µs delay, showed comparable transient performance but a steady-state output voltage ripple five times larger, which the authors call unacceptable for the target application.

These performance claims come from simulation, not from a built and measured prototype. The Monte Carlo study uses a high-level model, and the circuit-level study uses manufacturer component models in LTSpice. The paper reports that circuit non-idealities have negligible impact because the circuit-level responses mostly overlap with the high-level simulations, but this conclusion is bounded by the accuracy of those models and by the specific component set chosen.

The stability claim is also formal: the paper proves stability of the feedback system's equilibrium point robustly with respect to disturbances. That proof concerns the nominal control law and disturbance robustness, not the parametric uncertainty intervals explored only through simulation.

A design trade-off between region count and switching speed

The paper's central practical message is a trade-off rather than a universal replacement. The analog implementation becomes feasible because the explicit MPC law is reduced to 2 unsaturated regions and 4 non-trivial inequalities for the buck case, which maps to a four-channel multiplexer, 2 generalized adders, and 5 comparators. The reduction is what makes a fully analog circuit with commercial low-latency parts possible at 500 kHz.

The comparison that matters most is against VMC, the established strategy compatible with high-frequency operation. The analog explicit MPC does not win on undershoot, where the two are close (2.6% versus 2.4%), but it settles far faster on both the rising edge (2.5 µs versus 10 µs) and the falling edge (42 µs versus over 200 µs). A designer weighing this approach should therefore focus on recovery speed under load steps at high switching frequency, while accepting a steady-state error of up to 10 mV and relying so far on simulation evidence rather than measured hardware.

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