What limits the future scaling of 3D NAND flash technology?

Why lithography is no longer the main limit

For most of the past decade, 3D NAND density gains came from four largely independent scaling vectors working together: vertical stacking of wordline layers, lateral in-plane partitioning of the array, logical scaling of bits per cell, and architectural or packaging schemes. The paper states that current-generation products reach areal densities approaching 28 Gb/mm2, and that this came from the interplay among those four levers rather than any one of them in isolation.

The paper argues that this trajectory is changing. As layer counts approach the kilolayer regime, the constraints shift from patterning to charge transport, variability, reliability, and shrinking operating margins. The authors describe this as a transition analogous to post-Moore logic, where performance is no longer limited by patterning but by transport, variability, and energy efficiency. That framing is the paper's central claim, not a measured device result.

The continuous nitride layer drives charge loss

In charge-trap flash, charge is stored in a silicon-nitride layer inside an oxide-nitride-oxide stack, and multiple cells are vertically aligned along a cylindrical polysilicon channel. Unlike floating-gate devices, where the storage node is physically isolated, this nitride layer is continuous across all cells in a string. The paper identifies lateral charge migration as the dominant reliability constraint in modern 3D NAND precisely because that continuity permits trapped charge to redistribute through diffusion and trap-to-trap transport.

The driving force is the internal electric-field gradient between adjacent wordlines, most pronounced when a programmed cell borders an erased neighbor. The paper notes that even a small displacement of charge induces a measurable threshold-voltage shift, because the absolute storage volume per cell decreases with each scaling generation. As z-pitch narrows, physical separation between trapping regions decreases and the field landscape becomes increasingly non-uniform, producing early-time retention loss and enhanced neighbor-cell disturbance, particularly in TLC and QLC modes with intrinsically narrow state margins.

The paper states that architectural approaches such as trap-layer segmentation and algorithmic techniques such as threshold-voltage nearing can mitigate field gradients but cannot fully suppress the underlying transport mechanism. It concludes that lateral charge migration is a fundamental limitation of the continuous charge-trap concept, one that ferroelectric storage, with its intrinsically confined polarization switching, is uniquely suited to overcome.

Coupling, disturb, and transport compound the margin loss

Electrostatic coupling between adjacent cells is a second consequence of aggressive z-scaling. As wordline spacing decreases, fringing fields from programming and read-pass biases perturb the channel potential of neighboring cells, and the floating polysilicon channel, with no direct substrate reference, is particularly susceptible. The paper reports this manifests as program disturb and read-pass-induced threshold-voltage shifts, with the strongest effects between adjacent wordlines when the victim cell is erased.

Read disturb grows in severity as the number of stacked layers increases. During a read, all non-selected cells must be biased at a pass voltage of roughly 6 to 8 V to maintain channel conduction, and repeated application imposes cumulative electric-field stress across the tunnel oxide, inducing gradual charge injection into cells never directly written. The paper notes this mechanism is particularly relevant for active-storage and compute-in-memory workloads, where read frequency exceeds cold-storage tiers by orders of magnitude.

String current degradation is a separate transport constraint. As the number of cells in a NAND string grows, the series resistance of the polysilicon channel increases proportionally, causing total read current to saturate. In long strings this compresses the current separation between programmed states, reducing the sense-amplifier margin available to distinguish multi-level threshold-voltage distributions. Grain-boundary-dominated conduction in poly-Si channels compounds the effect through carrier scattering and trap-assisted transport. The paper states that architectural mitigations such as sub-block partitioning and dual-deck bonding can shorten effective string length, but at the cost of additional select transistors, process steps, and die area.

Thermal and variability effects tighten the window

Tall 3D NAND stacks exhibit pronounced thermal non-uniformity during operation. Because the multi-layer oxide-metal stack has low thermal conductivity, Joule heating dissipates unevenly, producing temperature gradients of several kelvins across the stack height. Cells near the center of a tall string experience higher local temperatures than those at the extremes, leading to position-dependent shifts in threshold voltage, retention, and read current.

The paper states that this self-heating compounds the cross-temperature effect, in which programming at one ambient temperature and reading at another shifts threshold-voltage distributions relative to fixed read references. The combined thermal perturbation worsens with each additional layer and becomes particularly acute in QLC devices, where state margins are already minimal.

Charge-trap NAND also contends with a broadening set of variability sources that compress the usable threshold-voltage window. Intrinsic randomness arises from the small number of electrons stored in scaled cells, making threshold voltage sensitive to individual trapping or detrapping events. The paper identifies lateral charge migration and threshold-voltage window collapse as the most fundamental limits, because they directly constrain retention and multi-level operation, the two properties on which every NAND application ultimately depends. Electrostatic coupling, read disturb, and transport degradation compound these primary bottlenecks.

Why one device roadmap cannot serve all tiers

The paper's central argument is that NAND demand is not monolithic, and that this heterogeneity precludes any monolithic scaling strategy. Cold storage in hyperscale datacenters demands maximum bit density and long-term retention with infrequent access. Active storage for AI training and inference requires sustained throughput and robust endurance under continuous cycling. Emerging paradigms such as high-bandwidth flash and big-accelerator memory co-package NAND alongside compute to reduce data-movement overhead, and compute-in-memory architectures repurpose the NAND array itself as a computational substrate.

Each tier places distinct, and in some cases competing, demands on endurance, retention, operating voltage, variability, and bandwidth. The paper notes that some tiers may also favor fundamentally different operating modes: whereas cold storage continues to reward aggressive multi-level scaling, latency-critical inference buffers may increasingly favor SLC-like operation to maximize read speed, sensing margin, and quality of service.

The authors argue that sustaining NAND scaling will therefore require application-specific co-optimization rather than a monolithic device roadmap. In this framework, conventional charge-trap flash, ferroelectric storage, alternative channel materials, and system-level integration are best viewed as complementary solutions targeted to distinct tiers of data-centric computing.

Ferroelectric and channel-level interventions address specific bottlenecks

The paper proposes a hierarchy of interventions rather than wholesale replacement of charge-trap flash. At the storage-mechanism level, ferroelectric gate stacks with BOXCUT architectures directly address the dominant bottlenecks of charge delocalization and margin collapse, positioning Fe-NAND as the enabling technology for active-storage and compute-in-memory tiers. This is the authors' proposed pathway, not a demonstrated production result.

At the channel level, two-dimensional semiconductors and amorphous oxide semiconductors are presented as ways to eliminate the grain-boundary transport limitations that constrain string current in kilolayer poly-Si channels. The paper states that this transport constraint provides direct motivation for alternative channel materials that offer higher mobility free from grain-boundary scattering.

At the system level, high-bandwidth flash and big-accelerator memory mitigate the data-movement bottleneck that increasingly limits AI workloads, while compute-in-memory repurposes the NAND array itself as a computational substrate. Throughout, the paper keeps charge-trap flash as the cost-optimized baseline for high-density cold storage, where its manufacturing maturity is unmatched.

Simulation must span atoms to system reliability

Evaluating whether a ferroelectric gate stack paired with an IGZO channel can meet the endurance, retention, and variability targets for a specific application tier, and whether its process integration is compatible with existing charge-trap-flash manufacturing lines, requires a seamless flow from atomistic calculations through device TCAD to system-level reliability projection. The paper calls this multi-scale integration a necessity for the co-design framework it advocates, not merely a convenience.

Machine learning is increasingly intertwined with this simulation hierarchy. The paper describes applications ranging from unsupervised clustering of homogeneous memory regions for region-based error correction, to supervised models of program-disturb behavior, to neural-network-based optimization of cell programming and trap-energy distributions. These AI-assisted approaches replicate the predictive accuracy of full TCAD simulations at substantially lower computational cost, accelerating the design cycle for next-generation devices.

The paper identifies current gaps in mesoscale trap-transport models and the limited transferability of machine-learning surrogates across process nodes as among the most pressing technical challenges facing the NAND community. These gaps qualify how far the proposed co-design framework can currently be evaluated.

The portfolio split is the paper's real conclusion

The paper's closing position is that no single innovation will suffice and no single application defines the requirements. In practice, it expects future NAND to evolve as a portfolio: dense multi-level charge-trap storage for cold data, SLC-like operation for latency-sensitive inference tiers, and emerging devices such as ferroelectric NAND and advanced channel materials where margin, voltage, or computational functionality become the dominant design constraints.

The most decision-relevant distinction in this paper is not which mechanism is worst in isolation, but which tier each mechanism is meant to serve. Lateral charge migration and threshold-voltage window collapse are identified as the most fundamental limits because they constrain retention and multi-level operation, which is exactly why the paper assigns ferroelectric storage to active-storage and compute-in-memory tiers rather than to cold storage. String current degradation motivates alternative channel materials for kilolayer poly-Si channels. Read disturb matters most where read frequency exceeds cold-storage tiers by orders of magnitude.

The paper also frames a shift in NAND's role: it argues that NAND evolves from a passive repository into an active element of the computational data path, where storage, transport, and computation are increasingly co-located. That claim is the authors' forward-looking interpretation, and the paper presents it as a Perspective argument rather than as a measured outcome. The practical threshold it leaves readers with is tier-specific: match the storage mechanism, channel material, and integration scheme to the endurance, retention, voltage, and bandwidth demands of the specific data-centric tier, rather than assuming a single device roadmap can carry all of them into the kilolayer regime.

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