Mining Hardware Truths: Automated Assertion Extraction via Sequential Data Mining

TL;DR

In the high-stakes world of SoC (System-on-a-Chip) design, functional verification is the ultimate bottleneck. This paper presents a "Reverse Engineering" approach that automatically extracts sequential hardware assertions from simulation traces. By treating signal changes as an event sequence and applying data mining algorithms, the authors can discover the underlying "rules" of a design without manual intervention.

The Motivation: Verification's Manual Burden

Verification engineers spend countless hours writing assertions to monitor forbidden behaviors. While Assertion-Based Verification (ABV) is powerful, it suffers from a major flaw: it assumes the engineer perfectly understands the specification.

Prior works like IODINE attempted to automate this but were often restricted to a fixed catalog of simple invariants (e.g., "Signal A is always one-hot"). They struggled with sequential complexity—patterns where Event A triggers Event B after an arbitrary number of cycles. This paper aims to bridge that gap by using Spatio-Temporal Data Mining.

Methodology: From Traces to Episode Rules

The proposed methodology follows a structured pipeline: Signal Selection $\to$ Event Encoding $\to$ Episode Mining $\to$ Rule Evaluation.

1. Defining the "Episode"

The authors define an Event as a unique combination of signal values in a clock cycle. A simulation trace becomes an Event Sequence.

• Episode: A maximum-size subsequence that appears frequently.
• Slide Window: To keep the search space manageable, the engine only looks for correlations within a specific time window.

2. The Extraction Engine

The core of the system is the Assertion Extraction Engine. It uses a two-step "Support-Confidence" framework borrowed from market basket analysis:

1. Support: How often does this pattern occur? (Filters out noise).
2. Confidence: If Pattern X occurs, how likely is it that Pattern Y follows? (Determines the "strength" of the rule).

Fig. 1: The architecture of the assertion extraction methodology.

Experimental Evidence: Cracking the AMBA Protocol

To validate the approach, the authors applied it to the AMBA 2.0 AHB Protocol, a standard for high-performance on-chip communication.

Iterative Discovery

The engine searched through 7,540 clock cycles of data. One key insight was the Support-Level Scaling. By starting at a high support level (8 occurrences) and moving down to 4, the engine could find "perfect" patterns first and then pick up variations caused by bus wait states or busy signals.

Fig. 2: The AHB simulation environment consisting of masters, slaves, and an arbiter.

Results Table

As shown in the table below, the "Rules" extracted at lower support levels successfully covered complex transactions like WRAP4 and INCR16, which might have appeared less frequently or with more timing variance than simple transfers.

Fig. 3: Summary of transaction coverage across different support levels.

Critical Analysis & Future Outlook

The beauty of this approach lies in its agnosticism. It doesn't need to be "told" what an AHB transaction looks like; it discovers the transaction sequence because the hardware logic consistently repeats it.

Limitations:

• Signal Selection: The method still relies on a user to select "interesting" signals. If a vital control signal is omitted, the engine will miss the logic.
• Trace Quality: If the testbench doesn't exercise a specific corner case, the data mining engine cannot "invent" the corresponding assertion.

The Road Ahead: This technology could eventually be integrated directly into waveform viewers. Imagine a debugger that doesn't just show you "what happened," but automatically highlights "this sequence happens 99% of the time, but it just failed here"—instantly pinpointing the anomaly.

Conclusion

This work proves that data mining is not just for consumer behavior; it is a surgical tool for hardware verification. By transforming traces into structural rules, we move closer to a future where hardware can effectively "verify itself."