CUP: Bridging the Data Gap in DFM with Generative Layout Synthesis

Layout pattern generation and legalization with generative learning models

2020-11-02
Xiaopeng Zhang, James P. Shiely, Evangeline F. Y. Young
Summary
Problem
Method
Results
Takeaways
Abstract

This paper introduces CUP (CU Pattern generation and legalization), a generative learning framework designed to synthesize diverse and DRC-clean VLSI layout patterns. It utilizes a Variational Convolutional Auto-Encoder (VCAE) for topology generation and a CGAN-based model, LegalGAN, to automate design rule legalization and style refinement.

TL;DR

VLSI layout pattern synthesis is critical for Design for Manufacturing (DFM) but is often limited by data scarcity and complex Design Rule Check (DRC) constraints. CUP (CU Pattern generation) introduces a robust framework combining Variational Convolutional Auto-Encoders (VCAE) and LegalGAN to generate high-diversity, DRC-clean, and "realistic" 2D patterns, achieving a 97% reduction in design rule violations compared to raw generative outputs.

Problem & Motivation: The Data Scarcity in Silicon Development

In the early stages of a new technology node (e.g., 3nm or 2nm), layout libraries are practically non-existent. However, DFM tools like hotspot detectors and Optical Proximity Correction (OPC) engines require massive datasets to train.

Prior works relied on simple data augmentation (flipping/rotating) or random generators, which fail to capture the inherent style of actual IC designs—the subtle spatial correlations produced by place-and-route tools. The challenge is two-fold:

  1. Diversity: Generating "new" patterns that aren't just copies of the old ones.
  2. Legality: Ensuring these new patterns satisfy strict nanometer-scale design rules.

Methodology: The CUP Framework

The authors break layout patterns into Squish Representations (Topological matrices + Geometric vectors). Their CUP framework operates on the topology in three distinct phases:

1. Topology Generation (VCAE)

Rather than a standard VAE, the authors use a VCAE with Residual Blocks to capture complex 2D spatial features. By applying Gaussian perturbation in the latent space, they can "tweak" a real layout into a completely new, yet stylistically similar, version.

Model Architecture

2. Design Rule Legalization (LegalGAN)

Generative models often produce "blurry" or slightly misaligned shapes that fail DRC. LegalGAN is a Conditional GAN (CGAN) that acts as a "refiner." It is trained to map the blurry output of the VCAE decoder back to a sharp, legal layout. By iteratively applying LegalGAN, patterns are "pushed" toward a legal state.

3. Style Detection

To ensure patterns aren't just legal but also "realistic" (resembling layouts produced by commercial EDA tools), CUP incorporates an Anomaly Detection model. It filters out patterns that satisfy DRC rules but "look" wrong (e.g., random noise or patterns from the wrong technology layer).

Style Detection

Experimental Validation

Using ICCAD 2014 contest benchmarks, the authors demonstrated that CUP significantly expands the design space.

  • Diversity Boost: The Shannon Entropy (Diversity) of the library jumped from 6.6 (basic patterns) to 9.86 (generated).
  • Legalization Efficacy: In just 30 iterations, LegalGAN increased the legality rate from 2.1% to over 84%.

Refinement Process Visualizing the iterative transition from a blurry raw generation to a sharp, DRC-clean topology.

Critical Insight & Conclusion

The core value of this research lies in its recognition that legality and style are distinct. While design rules are explicit, "design style" is implicit. By using a GAN-based refiner (LegalGAN) and an adversarial style detector, the authors successfully bypassed the manual coding of complex design rules into the neural network architecture itself.

Future Outlook: As we move toward AI-driven EDA, frameworks like CUP could enable "zero-shot" DFM tool development for future process nodes without waiting for engineers to manually construct layout libraries.

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Contents
CUP: Bridging the Data Gap in DFM with Generative Layout Synthesis
1. TL;DR
2. Problem & Motivation: The Data Scarcity in Silicon Development
3. Methodology: The CUP Framework
3.1. 1. Topology Generation (VCAE)
3.2. 2. Design Rule Legalization (LegalGAN)
3.3. 3. Style Detection
4. Experimental Validation
5. Critical Insight & Conclusion