ML-BATC: Optimizing Semiconductor Batch Scheduling via Parameter Learning

TL;DR

Scheduling parallel batch machines in semiconductor fabrication is an NP-hard challenge exacerbated by incompatible job families and dynamic arrivals. This paper presents a hybrid methodology that keeps the speed of the Batched Apparent Tardiness Cost (BATC) dispatching rule but uses Neural Networks and Decision Trees to intelligently "tune" its sensitive look-ahead parameter ($k$). The result? Schedules nearly as good as brute-force optimization but generated in real-time.

Problem & Motivation: The "Waiting" Paradox

In the diffusion and oxidation areas of a wafer fab, machines process "batches" of jobs. However, two constraints make this difficult:

1. Incompatibility: Only jobs from the same family can be processed together.
2. Unequal Ready Times: Jobs arrive at different times.

The core dilemma is the Waiting Paradox: Should a machine start a half-empty batch now to save time, or wait for a future arrival to increase efficiency? The classic ATC (Apparent Tardiness Cost) rule handles this using a look-ahead parameter ($k$). If $k$ is too small, the system becomes too focused on processing times; if too large, it focuses solely on due-date slack. Finding the "Goldilocks" value of $k$ usually requires expensive manual simulation or exhaustive search.

Methodology: The Machine Learning Strategy

The authors treat the parameter setting as a regression/classification problem.

1. Feature Engineering (The System State)

Instead of raw data, they define five high-level descriptors of the factory's current state:

• $T$ & $ildeT$: Tightness of due dates and ready times.
• $R$ & $ildeR$: Range/variance of due dates and ready times.
• $\mu$: The batch-machine factor (an indicator of system load).

2. Architecture

They compared two primary ML models to predict $k$:

• Multi-layer Perceptron (MLP): A feed-forward neural network with 3 to 7 hidden nodes.
• Inductive Decision Trees (ID3): Which partitions the attribute space into hypercubes to assign the best $k$ class.

Note: The model uses the system features as inputs $a_j$ to minimize the weighted sum of tardiness.

Experiments & Results

The researchers tested the models against a "Near-Optimal" baseline (calculating every possible $k$ value).

Key Findings:

• Near-Optimal Performance: The IDT approach with 25 classes achieved a Mean Square Error of only 0.0259 against the theoretical optimum.
• Generalization: Even when tested on scenarios with different batch sizes or 12 job families (vs. the 3 used in training), the models remained robust.
• Efficiency: Training takes minutes, but inference (deciding $k$) takes milliseconds, making it suitable for high-velocity manufacturing environments.

Graph: Impact of Due Date Tightness (T) on performance. The ML-predicted curves (twt_inf) closely track the optimal patterns.

Critical Analysis & Conclusion

Takeaway

The genius of this work isn't in a new complex algorithm, but in improving a simple one. By using ML to "supervise" a dispatching rule, we get the best of both worlds: the reliability of industry-standard rules and the adaptive "intelligence" of modern AI.

Limitations & Future Work

• Static vs. Incremental: The current ID3 setup is static. In a real fab, data is a stream. The authors suggest moving to ID5R (Incremental Induction) in the future.
• Setups: The study assumes incompatible families, but future models need to handle sequence-dependent setup times, where the "cost" of switching between families isn't constant.

This paper serves as an early but foundational proof that machine learning can act as a high-level "tuner" for classical industrial engineering heuristics.